As is known, in so-called embedded phase-change memories (ePCMs), storage of information is obtained by exploiting phase-change materials, having the property of being able to switch between phases that have resistivities of considerably different value. In particular, these materials may switch between an amorphous phase, with high resistivity, and a crystalline or polycrystalline phase, with low resistivity. Consequently, in a phase-change memory cell it is possible to associate a different value of a datum stored in the cell to a respective amorphous or crystalline phase, and to a corresponding resistivity, of a corresponding phase-change memory element.
For instance, it is possible to use elements of group VI of the periodic table, such as tellurium (Te), selenium (Se), or antimony (Sb), referred to as “chalcogenides” or “chalcogenic materials,” to form phase-change memory elements. An alloy made up of germanium (Ge), antimony (Sb), and tellurium (Te), known as GST (having chemical composition Ge2Sb2Te5) currently finds wide use in such memory elements.
Phase switching in a memory element may be obtained by locally increasing the temperature of the region of phase-change material, for example, by causing passage of a programming electric current through resistive electrodes (generally known as “heaters”) arranged in contact with the region of phase-change material. The electric current, by the Joule effect, generates the temperature profile required for phase change.
In particular, when the phase-change material is in the amorphous state, with high resistivity (the so-called RESET state), it is required to apply a first current pulse (the so-called SET pulse) of a duration and amplitude such as to enable the material to cool slowly. Subjected to this treatment, the phase-change material changes state and switches from the high-resistivity state to a low-resistivity crystalline state (the so-called SET state). Conversely, when the phase-change material is in the SET state, it is required to apply a second current pulse (the so-called RESET pulse) of large amplitude and short duration so as to cause the material to return into the high-resistivity amorphous state.
Reading of the datum stored in a memory cell may be carried out by applying to the phase-change material memory element a voltage sufficiently low as not to cause sensible heating thereof, and then by reading the value of the current flowing in the memory cell. Given that the current is proportional to the conductivity of the phase-change material, it is possible to determine in which phase the material is, and thus determine the datum stored in the memory cell.
In particular, a reading architecture for PCM devices is known, of a differential type, where two memory cells of opposite states are associated to each bit of a word to be read (made up, in a known way, of an appropriate number of bits). For instance, a bit has a value “1” if a first memory cell (so-called “direct memory cell”) and a second memory cell (so-called “complementary memory cell”) associated to the bit are, respectively, in the SET state and in the RESET state, and has a value “0” if the first and second memory cells are, respectively, in the RESET state and in the SET state. Differential-reading architectures afford advantages in terms of reliability, in so far as the datum is stored in a redundant way and moreover do not require generation of a reference current in so far as reading is carried out simply by comparing the currents flowing in the cells associated to a same bit.
In a known manner, the memory cells are arranged in a memory array in rows formed by word lines (WL) and columns formed by bit lines (BL).
As shown schematically in FIG. 1, each memory cell 2 comprises a phase-change element 2a and a selector element 2b, for example a MOSFET or (as illustrated in the figure) a bipolar junction transistor (BJT), which is electrically coupled to the heater associated to the phase-change element 2a (here not illustrated) so as to enable selective passage of a programming or reading electric current.
In the case of selector elements of a BJT type, the phase-change element 2a is coupled between the emitter terminal of the BJT, in the example of a pnp type, of the respective selector element 2b and a respective bit line BL. In addition, the base terminal of the selector element 2b is electrically coupled to a respective word line WL. The base terminals of the selector elements 2b of the memory cells 2 of a same row are coupled to a same word line WL, and the phase-change elements 2a of the memory cells 2 of a same column are coupled to a same bit line BL. The collector terminals of the BJTs of the selector elements 2b are set at a reference voltage, for example the ground reference voltage GND.
Use of selector elements 2b of a BJT type, to which the present discussion will make specific reference, affords some advantages over MOSFET technology, such as a reduction of the overall area occupied by the memory cells 2 and a resulting greater density of integration of the memory device.
However, use of selector elements of a BJT type requires, as compared to the use of MOSFETs, an appropriate consideration of the base currents of the respective BJTs, which flow along the word lines WL and may determine undesirable voltage drops along the same word lines WL.
FIG. 2 shows, in this regard, a memory array 3 of a memory device 1, of the phase-change type, the memory cells 2 of which are coupled to respective word lines WL (aligned in rows) and respective bit lines BL (aligned in columns). The phase-change elements 2a of the memory cells 2 are here represented schematically by respective resistor elements.
In particular, FIG. 2 shows the parasitic (or line) resistances associated to the bit lines BL, designated by RBL, and to the word lines WL, designated by RWL. Further represented are the base parasitic resistances of the BJTs of the selector elements 2b of the memory cells 2, designated by RB.
In the solution illustrated in FIG. 2, the base terminals of the selector elements 2b of a same row are coupled to a same metallization line, which is contacted at regular intervals, in the example every four memory cells 2, by a respective word line WL (in a way that will be evident to a person skilled in the field, the word lines WL are arranged at a higher metallization level than the base-metallization lines, in the layout of the memory array 3).
The memory device 1 further comprises, as illustrated schematically, a row decoder 4 and a column decoder 5, configured to address and bias in a suitable manner the word lines WL and the bit lines BL, respectively, each time selected for the (programming and reading) memory operations.
In particular, during the programming (or modify) and reading operations, a word line WL, addresses and selected, is typically biased at the ground reference voltage GND (in the example, the BJTs are of a pnp type). When not selected, the same word line WL is, instead, biased at a positive voltage, of an appropriate value.
Therefore, an electric current flows along a selected word line WL (with a value, which may even be high, that depends on the memory operation performed) that determines a line voltage drop due to the resistances associated to the word line WL (which are constituted by the line parasitic resistance RWL and the base parasitic resistance RBL). The biasing conditions of the memory cells 2 thus vary along a same word line WL, in an undesirable way, as a result of the voltage drop, according to the position occupied in the memory array 3.
In order to limit the above drawback, it has been proposed to split the memory array 3 into portions, so-called tiles, each tile comprising a certain number (for example, 256, 512, or 1024) of local word lines and local bit lines, which constitute portions of respective rows and columns of the entire memory array 3.
Selected words are in this case made up of a certain number of bits that are distributed on different tiles, thus limiting the number of memory cells selected and, consequently, the effect of the voltage drops on the word lines, within each tile.
Although advantageous, the above solution requires, however, multiplexing operations during reading and row address decoding operations that enable selection of the addressed memory cells 2 in the various tiles in order to reconstruct the data word. In general, it is rather complex to define a row decoding architecture enabling addressing of the memory cells 2 as desired and at the same time not entailing a significant burden in terms of manufacturing complexity and area occupation.
In greater detail, FIG. 3 shows a portion of the memory array 3 of the memory device 1, which comprises a group, in the example, of five tiles, arranged alongside one another on a same row; each tile, designated by 6, is formed, as indicated previously, by a certain number of memory cells, arranged in local word lines WL and local bit lines BL (here not illustrated).
The row decoder 4 in this case comprises: a main row decoding unit 8, associated to the group of tiles 6, configured to supply address-decoding and biasing signals, on the basis of address signals received at the input; and a number of local row decoding units 9, one for each tile 6 of the group, coupled to the main row decoding unit 8. In particular, the local row decoding units 9 have the function of locally selecting the word lines WL, i.e., setting to the ground reference voltage GND the same word lines WL, within the respective tiles 6.
Likewise, the column decoder 5 in this case comprises a plurality of local column-decoding units 10, one for each tile 6, which enable selection and biasing of the local bit lines BL associated to which are the memory cells that are to be read, and their connection to respective sense amplifiers (SAs) 11, configured for comparison of the reading currents of the (direct and complementary) memory cells associated to each bit of the data word.
In the example, thirty-two memory cells (i.e., sixteen data bits, given the differential reading) are read for each tile 6, so that sixteen sense amplifiers 11 are present for each tile 6. The resulting reading is made up of a double word, each word being constituted by thirty-two data bits plus seven bits of error-correction code (ECC) plus one redundancy bit. Thus, in total, 40+40 bits are read corresponding to 2 words, which correspond to 160 cells physically addressed on the aforesaid hypothesis of differential reading.
It should be noted that the number of memory cells read within each tile 6 in general depends on a maximum voltage drop that may be withstood on the word line WL; for example, in the case illustrated, reading of thirty-two memory cells may entail, in a real case, a voltage drop of approximately 100 mV on the local word line WL of the tile 6.